The goal of register renaming is to allow blocks of instructions to be executed out of order.
Take for example the following instructions
1. divd r5, r7, r12
2. addd r6, r7, r8
3. sd r6 0(r1)
4. subd r8, r14, r12
5. muld r6, r15, r8
Looking at these you can see that without register renaming you have to run the instructions in the sequence 1,2,3,4,5. However if you note, lines 4 and 5 don't depend on 1,2,3. The issue is that if they run before 1,2,3 they will clober the data that 1,2,3 are trying to calculate with.
If we simply rename the registers r8 and r6 in 4,5 we can remove that dependency.
This type of dependency is called a false dependency, because the only thing preventing them from running out of order is simply you are using the same registers, not the same data.
Now look at this:
1. divd r7, r5, r12
2. addd r6, r7, r8
3. sd r6 0(r1)
4. subd S, r14, r12
5. muld T, r15,S
Now the instructions 1,2,3 can occur independent of 4,5. Since there are Read after Writes (RAW), and Write after Reads (WAR) the instructions within the 1,2,3, they must occur in order.
for example, the following orders are now valid.
a. 1,4,2,3,5
b. 4,1,2,3,5
c. 1,2,4,5,3
...
The only requirement now is that 1,2,3 occur in succession, and 4,5 occur in succession for example
the following executions are invalid
a. 2,1,4,5,3
b. 3,1,4,2,5
The reason is because the instructions are data dependent on each other "in" those blocks of code.
Any questions? Just go ahead and ask.
